Integrated circuit memory

ABSTRACT

An integrated circuit memory is provided wherein an array of memory elements is addressed by a decoder circuit responding to an address signal. The decoder circuit includes a plurality of sections, each one thereof being used to address a different section of the array. A decoder section selector is provided which, in response to the addressing signal, determines the section of the array being addressed and electrically couples the one of the plurality of decoder circuit sections which is coupled to such addressed array section to a power source while electrically decoupling the remaining section of the decoder circuit from such power source. With such arrangement, only a portion of the decoder circuit is electrically coupled to the power source when addressing the array thereby reducing the power consumption of the integrated circuit memory.

BACKGROUND OF THE INVENTION

This invention relates generally to integrated circuit memories and moreparticularly to memories having a relatively large storage capacity.

As is known in the art, it is generally desirable to increase the memorystorage capacity of integrated circuit memories. However, as the memorycapacity of the integrated circuit increases the power requirements ofthe circuit correspondingly increases. For example, in a bipolarread-only memory (ROM) circuit the cross points of rows and columns ofconductors correspond to the memory locations of the circuit. Thepresence, or absence, of an electrical connection between the row andcolumn conductors at a particular cross point determines the logicalstate of the bit stored at the corresponding memory location. Onceprogrammed, the data is read from a particular location by couplingaddress signals to row and column decoders to select the particular rowand column conductors which "cross" at the addressed location. As isknown in the art, for such memory circuit these decoders generallyrequire power for their operation and, as the size or capacity of thememory circuit increases, the size of the decoders correspondinglyincrease in order to provide addressing to an increased number of rowsand columns of conductors. More particularly, the decoders generallyinclude logic gates and diode matrices so that when a larger number ofgates and/or matrices is used in the decoders, extra power is consumedby the additional resistors in such gates and matrices. One way whichmay be used to decrease the power consumption of the increased capacitydecoders is to increase the resistance of these resistors; however, theincreased resistance increases the switching time of the decoder therebyresulting in a more slowly responding ROM circuit.

SUMMARY OF THE INVENTION

In accordance with the present invention, an array of memory elements isprovided with a decoder circuit responsive to an address signal forselectively addressing the memory elements in the array, such decodercircuit having a plurality of sections each one thereof addressing adifferent section of the array. A decoder section selector is alsoprovided for electrically coupling the one of the decoder sections whichis addressing the array in response to the address signal to a powersource while electrically decoupling the remaining non-array addressingdecoder sections from such power source.

In a preferred embodiment of the invention, the decoder circuit respondsto a N-bit address signal to address one of 2.sup.(N) rows of the arrayof memory elements with each one of sections of the decoder circuitaddressing a different one portion of the rows. The decoder sectionselector responds to the addressing signal to couple the one of thedecoder sections which is coupled to the section of the array havingtherein the addressed row of memory elements while electricallydecoupling from the power source the remaining decoder sections. Thus,the decoder section selector responds to the addressing signals toidentify which section of the array of memory elements which containsthe row of elements addressed by the addressing signals and couplespower to only that one of the decoder sections. With such arrangement,by activating only a portion of the decoder circuit the powercomsumption of the memory circuit is reduced without increasing theresistance of resistors used in the decoder circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-mentioned and other features of the invention will now be moreapparent by reference to the following description taken together inconjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an integrated circuit memory inaccordance with the invention;

FIG. 2 is a schematic diagram of an exemplary one of the buffers used inthe integrated circuit memory of FIG. 1 and of a decoder sectionselector used in the integrated circuit memory of FIG. 1;

FIG. 3 is a schematic diagram of NAND gate sections of an X (row)address decoder circuit used in the integrated circuit memory of FIG. 1;

FIG. 4 is a schematic diagram of a diode decoder of a Y (column) addressdecoder circuit used in the integrated circuit memory of FIG. 1;

FIG. 5 is a schematic diagram of an integrated circuit memory inaccordance with an alternative embodiment of the invention; and

FIG. 6 is a schematic diagram of a diode decoder of a Y address circuitused in the integrated circuit memory of FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, an integrated circuit memory 10, here aread-only memory (ROM), is shown to include a memory array 12 of memoryelements 14, here an array of 65,536 memory elements 14 for storing8,192 different 8 bit digital words. The memory elements 14 are herearranged in 256 rows and 256 columns. The columns of memory elements 14are arranged in 8 different sets each one of such 8 sets having 32columns of memory elements 14. Thus, here the memory array 12 includes aplurality of, here 256, columns of conductors 16₀ -16₂₅₅ and a pluralityof, here 256, rows of conductors 18₀ -18₂₅₅ with memory elements 14,here diodes, electrically connected or electrically disconnected betweenthe rows and columns of conductors, as indicated, selectively inaccordance with the preprogrammed state of the memory array 12. As iswell known in the art, the presence, or absence, of an electricallyconnected diode represents the logical state or binary data stored atthe location in the memory array 12 corresponding to the "cross point"particular row and column conductor. Thus, the presence of a connecteddiode, such as diode 14a, indicates, for example, storage of a logical 1at the location represented by column conductor 16₀ and row conductor18₀ ; whereas the disconnected diode 14b represents a logical 0 at thelocation represented by column conductor 16₃₁ and row conductor 18₁₂₈.

The words stored in the memory array 12 are addressed by a 13 bitaddressing signal fed to terminals A₀ -A₁₂, with the least significantbit (LSB) of such addressing signal is fed to terminal A₀ and the mostsignificant bit (MSB) of such addressing signal is fed to terminal A₁₂.The 5 least significant bits of the addressing signal (i.e. those fed toterminals A₀ -A₄) are used to select one of the 32 columns of conductors16₀ -16₃₁ to 16₂₂₄ -16₂₅₅ in each of the 8 sets thereof while the 8higher order bits of the addressing signal (i.e. those fed to terminalsA₅ -A₁₂) are used to address one of the 256 rows of conductors 18₀-18₂₅₅. It is further noted that the memory array 12 is partitioned intotwo array sections 20₁ and 20₂, as indicated. Array section 20₁ includesrow conductors 18₀ -18₁₂₇, column conductors 16₀ -16₂₅₅ and the memoryelements 14 at the cross points thereof, while array section 20₂includes row conductors 18₁₂₈ -18₂₅₅, column conductors 16₀ -16₂₅₅ andthe memory elements 14 at the cross points thereof. It is here notedthat here when the most significant bit fed to terminal A₁₂ is a logical0 (i.e. a "low" voltage signal), one of the 128 conductors 18₀ -18₁₂₇ inarray section 20₁ is being addressed to thereby address the row ofmemory elements 14 in the array section 20₁ whereas when the logicalstate of the most significant bit fed to terminal A₁₂ is a logical 1(i.e. a "high" voltage), one of the rows of conductors 18₁₂₈ -18₂₅₅ inarray section 20₂ is being addressed to thereby address the row ofmemory elements 14 in array section 20₂.

The integrated circuit memory 10 includes an X (or row) address decodercircuit 22 fed by terminals A₅ -A₁₂ and a Y (or column) address decodercircuit 24 fed by terminals A₀ -A₄, as indicated. The Y (or column)address decoder circuit 24 includes a plurality, of here, 8 decodersections 24₁ -24₈, as indicated, each one of such decoder sections 24₁-24₈ being coupled to the corresponding one of the 8 different sets ofcolumn conductors 16₀ -16₂₅₅, as indicated. Further, each one of thedecoder sections 24₁ -24₈ in response to binary signals fed to terminalsA₀ -A₄, electrically couples one of the 32 column conductors coupled toeach one of the decoder sections 24₁ -24₈ to a corresponding one ofeight output terminals 0₁ -0₈, as indicated, thus reading the 8 bits ofstored data in the array 12 for the addressed word on terminals 0₁ -0₈.

The X (or row) decoder 22 and Y (or column) decoder circuit 24 includebuffer sections 26, 27 comprising a plurality of here 13 buffers 28₀-28₁₂ each one of such buffers 28₀ -28₁₂ being coupled to acorresponding one of the terminals A₀ -A₁₂ respectively, as indicated.Each one of the buffer circuits 28₀ -28₁₂ is identical in constructionand an exemplary one thereof, here buffer circuit 28₁₂ is shown indetail in FIG. 2 and will be described hereinafter. Suffice it to sayhere, however, that each one of the buffer circuits 28₀ -28₁₂ produces atrue and complement signal of the binary signal fed to such buffercircuit. Thus, buffer circuits 28₀ -28₁₂ provide "true" signals of thebits of the addressing signals fed to terminals A₀ -A₁₂ on lines A_(0')-A_(12') respectively and complement signals of the such bits on linesA_(0') -A_(12') respectively. The "true" and "complement" signals onlines A_(5') -A_(12') and A_(5') -A_(12') provided by the buffer section26 of the X address decoder circuit 22 are fed to a NAND gate decodersection 30, as shown. The NAND gate decoder section 30 includes aplurality of, here 2, NAND gate decoder sections 32₁, 32₂, as indicated.The details of the NAND gate decoder section 30 will be described indetail in connection with FIG. 3. Suffice it to say here however, thatNAND gate decoder section 32₁ is coupled to array section 20₁ of thememory array 12 while decoder section 32₂ is coupled to array section20₂ of memory array 12, as indicated. It is further noted that whileboth the true and complement signals on lines A_(5') -A_(11') and A_(5')-A_(11') are fed to both NAND decoder sections 32₁ and 32₂ only the"true" signal of the most significant bit fed to terminal A₁₂, i.e. thesignal on line A_(12') is fed to decoder section 32₂ while only the"complement" signal of the MSB (i.e. the signal on line A_(12')) is fedNAND gate decoder section 32₁. Further, each one of the NAND gatedecoder sections 32₁, 32₂ includes a power input terminal V'_(CC), thepower input terminal V'_(CC) of section 32₁ being coupled to a NAND gatesection selector 36 via line 34₁, and the power input terminal V'_(CC)of section 32₂ being coupled to the NAND gate section selector 36 vialine 34₂, as shown. Details of NAND gate section selector 36 will bedescribed in connection with FIG. 2. Suffice it to say here, however,that such NAND gate section selector 36 functions as a pair of switches37a, 37b which, in response to most significant bit of the addressingsignal fed to buffer 28₁₂ via terminal A₁₂ couples a +V_(CC) powersupply to either NAND gate decoder section 32₁ or, alternatively, NANDgate decoder section 32₂ selectively in accordance with the logicalstate of the most significant bit of the addressing signal. Thus, aswill be described in detail hereinafter if the logical state of the mostsignificant bit of the addressing signal fed to terminal A₁₂ is alogical 0 (i.e. a " low" voltage signal) thereby indicating that the rowof memory elements 14 being addressed is in memory array section 20₁ ofsuch array 12 the power supply +V_(CC) is electrically coupled, viaswitch 37a of NAND gate section selector 36, to decoder section 32₁ andis electrically decoupled, via switch 37b of NAND gate section selector36, from NAND gate section 32₂ ; on the other hand, if the mostsignificant bit of the addressing signal fed to terminal A₁₂ is alogical 1 indicating that the addressed row of memory elements 14 beingaddressed is in memory array section 20₂ then the +V_(CC) power sourceis electrically decoupled, via switch 37a of NAND gate section selector36, from the decoder section 32₁ and is electrically coupled, via switch37b of NAND gate section selector 36, to decoder section 32₂ to therebyallow such decoder section 32₁ to address one of the row of memoryelements 14 in the array section 20₂ of the memory array 12. In thisway, only one-half of the NAND gates in the NAND gate section 30 isenabled, or powered, during the reading operation of the integratedcircuit memory 10.

Referring now to FIG. 2, buffer circuit 28₁₂ is shown to include aninverter section 38 and a buffer 39. Inverter section 38 includes an PNPtransistor 40 having its base electrode coupled to terminal A₁₂, and toground through a Schottky diode 42, as shown. The base electrode oftransistor 40 is also coupled to the base electrode of a Schottkytransistor 44 through a Schottky diode 46, as indicated. The collectorelectrode of transistor 40 is connected to ground as shown. The emitterelectrode of transistor 40 is also coupled to the base electrode oftransistor 44 through a Schottky diode 50 and to a +V_(CC) supplythrough a resistor 52, as indicated. The collector electrode oftransistor 44 is also connected to the +V_(CC) source through a resistor56, as indicated, while the emitter electrode of such transistor 44 isconnected to ground through a resistor 58 and to the emitter electrodeof a Schottky transistor 60, as indicated. The base electrodes oftransistors 44 and 60 are electrically connected together as shown whilethe collector electrode of transistor 60 is connected to +V_(CC) throughresistor 62 and is also connected to the base electrode of transistor64. The collector electrode of transistor 64 is connected to +V_(CC) andthe emitter electrode thereof is connected to the collector electrode ofSchottky transistor 66 through a Schottky diode 68, as shown. The baseelectrode of transistor 66 is connected to the emitter electrodes oftransistors 44 and 60 and the emitter electrode of transistor 66 isconnected to ground, as shown. The collector electrode of transistor 66provides an output which is the "complement" of the binary signal fed toterminal A₁₂ and is connected to line A'₁₂, as shown. More particularly,if the logical signal at terminal A₁₂ is 1, that is a "high" voltagesignal, transistor 40 is placed in a nonconducting state. Diode 50 isforward biased placing transistors 44 and 60 in a conducting state withtransistor 66 being driven into saturation thereby producing a "low"voltage, or logical 0 signal at the collector electrode of transistor66. Conversely, when the logical state of the signal fed to terminal A₁₂is 0, or a "low" voltage signal, transistor 40 is placed into aconducting condition placing transistors 44, 60, and 66 in anon-conducting condition with the result that the collector electrode oftransistor 66 goes towards +V_(CC) or "high" producing a logical 1signal at the collector electrode of transistor 66.

The collector electrode of transistor 44 is coupled to buffer 39 andmore particularly to the base electrode of Schottky transistor 70. Theemitter electrode of transistor 70 is coupled to the base electrode ofSchottky transistor 72, and to ground through a resistor 74, as shown.The emitter electrode of transistor 72 is also connected to ground withthe collector electrode thereof coupled to the V_(CC) supply through aSchottky diode 74 and through a transistor 76, as shown. Transistor 76has its base electrode connected to the collector electrode oftransistor 70 and also to the +V_(CC) supply through a resistor 78, asindicated. The collector electrode of transistor 72 produces a "true"signal of the binary signal fed to the terminal A₁₂ and is connected toline A_(12'), as shown. More particularly, if the logical signal at A₁₂is 1 and transistor 40 is placed in a non-conducting condition as notedabove transistor 44 is placed in a conducting condition. Further, withsuch transistor 44 in a conducting condition a relatively low voltage isproduced at the collector electrode thereof, such low voltage beinginsufficient to place transistors 70 and 72 in a conducting conditionwith the result that a relatively "high" voltage is produced at thecollector electrode of transistor 72 and hence a logical 1 signal, or"true" signal of the bit fed to terminal A₁₂, is produced on lineA_(12'). Conversely, if the logical signal fed to terminal A₁₂ is 0,transistor 40 conducts while transistor 44 is placed in a non-conductingcondition. Therefore, the collector electrode of transistor 44 goestowards +V_(CC) and a relatively "high" voltage is thereby fed to thebase electrode of transistor 70 placing such transistor 70 in aconducting state and driving transistor 72 into saturation producing arelatively "low" voltage at the collector electrode of transistor 72 andhence the "true" signal of the logical signal fed to terminal A₁₂ isagain produced on line A_(12').

The signals produced at the collector electrodes of transistors 66 and72 are fed to the NAND gate section selector 36 via lines 80, 81,respectively, as shown. The NAND gate section selector 36 includes apair of transistors 82₁, 82₂ which function as switches 37a, 37b,respectively as described in connection with FIG. 1 above. The emitterelectrodes of transistors 82₁, 82₂ are connected to the +V'_(CC)terminals of the decoder sections 32₁, 32₂ via lines 34₁, 34₂respectively, as indicated in FIG. 1. The collector electrodes oftransistors 82₁ 82₂ are connected to the +V_(CC) supply. Line 80,connects the collector electrode of transistor 66 to the base electrodeof transistor 82₁ via a diode 86₁, as indicated. A resistor 88₁ isconnected between the base electrode of transistor 82₁ and the +V_(CC)source, as shown. Likewise, conductor 81 connects the collectorelectrode of transistor 72 to the base electrode of transistor 82₂ via adiode 86₂, as shown. Further, the resistor 88₂ is connected between the+V_(CC) source and the base electrode of transistor 82₂, as indicated.In operation when the logical signal (i.e. the MSB) fed to terminal A₁₂is logical 1 indicating that the memory elements 14 array in section 20₂(FIG. 1) is being addressed, then, as indicated above, a relatively"low" voltage is produced on line 80 forward biasing diode 86₁,producing an insufficient voltage at the base electrode of transistor82₁ to place such transistor 82 into a conducting condition therebyelectrically decoupling the +V_(CC) source from line 34₁ (and hence fromterminal V'_(CC) of section 32₁ (FIG. 1)); on the other hand, thelogical 1 signal produced at terminal A₁₂ produces a relatively "high"voltage on line 81 thereby reverse biasing diode 86₂ with the resultthat resistor 88.sub. 2 provides sufficient base current to transistor82₂ to forward bias such transistor 82₂ placing such transistor 82₂ in aconducting condition and thereby electrically connect the +V_(CC) supplyto line 34₂ and hence to terminal V'_(CC) of section 32₂ (FIG. 1) toallow such section 32₂ to address section 30₂ of array 12 as required bythe addressing signal. Conversely, when the logical signal at terminalA₁₂ is 0 transistor 82₁ is forward biased and the +V_(CC) source iselectrically coupled to line 34₁ and hence to section 32₁ to allowsection 32₁ to address array section 20₁ as required by the addressingsignal while transistor 82₂ is placed in a nonconducting condition tothereby electrically decouple the +V_(CC) source from line 34₂ (andhence from section 32₂).

Referring now to FIG. 3, NAND gate section 30 is shown to include indetail NAND gate decoder sections 32₁ and 32₂. Thus NAND gate section32₁ includes a plurality of NAND gates 100₀ -100₁₂₇ while NAND gatesection 32₂ includes a plurality of NAND gates 100₁₂₈ -100₂₅₅, as shown.Each one of the NAND gates 100₀ -100₂₅₅ is identical in construction andan exemplary pair thereof, here NAND gates 100₀, 100₁₂₈, are shown toinclude an input multi-emitter Schottky transistor 102 coupled to theV'_(CC) terminal via resistor 104. The collector electrode of transistor102 is connected to the base of Schottky transistor 106 which has itsemitter electrode connected to Schottky transistor 108, as shown andalso to ground through resistor 110, as shown. The emitter electrode oftransistor 108 is connected to ground, as shown. The collector electrodeof transistor 106 is connected to the +V_(CC) supply through a resistor112 while the collector electrode of transistor 108 is connected to theV_(CC) supply through a resistor 114 and Schottky diode 116. Further thecollector electrode of transistor 108 of gate 100₀ is connected to rowconductor 18₀, as shown. NAND gate 100₀ has the emitter electrodes oftransistor 102 coupled to the complement signals of the bits of theaddressing signal fed to terminals A₅ -A₁₂, as shown. Thus, transistor108 of gate 100₀ is driven into saturation only when all of the signalson lines A'₅ -A'₁₂ are "high" with the result that row conductor 18₀ is"low" or "addressed" only when the bits fed to terminals A₅ -A₁₂ are"low" on logical 0. Thus NAND gate 100₀ lowers the voltage on line 18₀to address such line 18₀ when the bits fed to terminals A₁₂ -A₅ are(00000000)₂ =(0)₁₀. Likewise NAND gate 100₁₂₇ is fed by lines A'₅ -A'₁₁and A₁₂ to lower the voltage on line 18₁₂₇ only when the bits fed toterminals A₁₂ -A₅ are 01111111=(127).sub. 10, respectively. In thegeneral case than NAND gates 100₀ -100₁₂₇ address or lower the voltageon row conductors 18₀ -18₁₂₇ when the bits fed to terminals A₁₂ -A₅ are(0)₁₀ -(127)₁₀, respectively. In like manner, NAND gates 100₁₂₈ -100₂₅₅address or lower the voltage on row conductors 18₁₂₈ -18₂₅₅ when thebits fed to terminals A₁₂ -A₅ are (128)₁₀ -(255)₁₀, respectively.Further, in response to the most significant bit of such addressingsignal, i.e. the bit fed to terminal A₁₂, the decoder selection section36 (FIGS. 1 and 2) couples the +V_(CC) supply, the +V'_(CC) terminal ofonly one of the two NAND gate decoder sections 32₁, 32₂ and moreparticularly couples such power source to the particular one of the pairof decoder sections 32₁, 32₂ which is addressing the addressed one ofthe row conductors 18₀ -18₂₅₅. Thus, as mentioned above, if the logicalstate of the most significant bit is 1 thereby indicating that theaddressed one of the row conductors 18₀ -18₂₅₅ is in array section 20₂,power is supplied from the +V_(CC) supply to the V'_(CC) terminal ofdecoder section 32₂ and such power source is electrically decoupled fromthe V'_(CC) terminal of section 32₁ ; conversely, if the mostsignificant bit of the addressing signal is 0 thereby indicating thatthe addressed one of the row conductors 18₀ -18₂₅₅ is in array section20₁ the section selector 36, in response to the logical state of themost significant bit, electrically decouples the +V_(CC) supply fromV'_(CC) terminal of decoder section 32₂ and electrically interconnectssuch supply to the V'_(CC) terminal of NAND gate decoder section 32₁. Itfollows then that during the reading operation of the ROM 10 onlyone-half of the 256 NAND gates 100₀ -100₂₅₆ is powered thereby reducingthe power consumption in resistors 104 of the 255 NAND gates 100₀-100₂₅₅.

Referring now to FIG. 4, an exemplary one of the eight identical decodersections 24₁ -24₈, here decoder section 24₁, is shown to include aconventional diode decoder matrix 120 coupled to the +V_(CC) powersource through resistors 122 as shown. In response to the "true" and"complement" signals of the five least significant bits of theaddressing signals, i.e. the bits fed to terminals A₀ -A₄, the diodedecoder matrix 120 coupled the +V_(CC) supply and one of the resistors122 to a one of the base electrodes of thirty-two Schottky transistors126₀ -126₃₁ selectively in accordance with the binary state of the bitsfed to terminals A₀ -A₄ to thereby turn such transistor to a conductingconductor. The collector electrodes of transistors 126₀ -126₃₁ areconnected together and to the input of a conventional inverter 128, asshown. The emitter electrode of transistors 126₀ -126₃₁ are connected tocolumn conductors 16₀ -16₃₁, respectively, as shown. Thus, here thetransistors 126₀ -126₃₁ are placed in a conducting conductor when thebits fed to terminals A₄ through A₀ are (00000)₂ =(0)₁₀ through (31)₁₀,respectively. Thus, when the bits fed to terminals A₄ -A₀ are 00001transistor 126₁ is placed in a conducting state to electrically couplecolumn conductor 16₁ to the input of inverter 128.

In operation then a particular one of the row conductors 18₀ -18₂₅₅ isaddressed or selected by the bits fed to terminal A₅ -A₁₂ and aparticular one of the 32 columns of conductors in each of the eight setsthereof: 16₀ -16₃₁ through 16₂₂₄ -16₂₅₅ is selected in response to thebits fed to the terminals A₀ -A₄ to thereby address one of the 256 eightbit words stored in array 12. For example, if the bits fed to terminalA₁₂ -A₀ are 1000000000001 the row conductor 18₁₂₈ is addressed, i.e.made "low" and column indicators 16₁, 16₃₃, 16₆₅, 16₉₇, 16₁₂₉, . . . and16₂₂₅ are addressed, i.e. coupled to the inverter 128 of decoderselectors 24₁ -24₈ and hence to the output terminals 0₁ -0₈,respectively. Thus, considering row conductor 18₁₂₈ and column conductor16₃₁ (FIG. 1) if there is a connected diode for the memory element 14bat the cross point of such row conductor and column conductor, thevoltage at the input to inverter 128 will be "low" producing a high orlogical 1 output at output terminal 0₁ ; however, if such diode is notconnected for memory element 14b such the voltage at the input inverter128 will be "high" and the voltage of the output 0₁ will be "low" orlogical 0. In any event, NAND gate of decoder section 32₁ will becoupled to the +V_(CC) supply via NAND gate section selector 36 when thebit fed to terminal A₁₂ indicates that the memory element 14 associatedwith row conductor 18₀ -18₁₂₇ is being addressed while NAND gate section32₂ is decoupled from such +V_(CC) supply and on the other hand when thebit fed to terminal A₁₂ indicates that the memory element 14 associatedwith columns 18₁₂₈ -18₂₅₅ are being addressed NAND gate section 32₂ iscoupled to the +V_(CC) supply through selector 36 while NAND gatesection 36 is decoupled from such +V_(CC) supply. It is noted that whileline A'₁₂ is shown coupled to NAND gate section 32₁ and line A'₁₂ isshown coupled to NAND gate section 32₂ since the control of each sectionis by power being or not being fed to lines 34₁, 34₂, the coupling oflines A'₁₂, A'₁₂ to section 32₂, 32₁ may be eliminated.

Referring now to FIG. 5, an alternative embodiment of the invention isshown. There the read-only memory circuit 10' has the Y or (column)decoder circuit 24' configured so that each one of the decoder sections24'₁ -24'₈ has two diode matrix sections 120a, 120b, as shown in FIG. 6.It is noted that a diode matrix section selector 36' (FIG. 5) isprovided. The selector 36' is fed by buffer 28'₄ in a manner equivalentto that of buffer 28₁₂ (FIG. 1); here however, selector 36' couples the+V_(CC) supply to either section 120a or 120b selectively in accordancewith the logical state of the bit fed to terminal A₄ (i.e. the MSB ofthe portion of the addressing signal used to address the columnconductors.) Thus, if the bit fed to terminal A₄ is a logical 0indicating that one of the sixteen column conductors in the eight setsthereof (i.e. one of the column conductors in the sets 16₀ -16₁₅, . . .16₂₂₄ -16₂₃₉) are being addressed selector 36' couples +V_(CC) to diodedecoder matrix 120a in the eight decoder sections 24'₁ -24'₈ via line121₁ while the matrix 120b in each of such eight sections is decoupledfrom +V_(CC). Conversely, if the logical bit fed to terminal A₄ islogical 1 indicating that the one of the column conductors 16₁₆ -16₃₁, .. . 16₂₄₀ -16₂₅₅ is being addressed selector 36' couples the +V_(CC)supply to diode matrix decoder 120b in each of the eight decodersections 24'₁ -24'₈ via line 121₂ while decoder 120a in each of theeight sections 24'₁ -24'₈ is decoupled from +V_(CC). In this manner,power is dissipated in only half of the resistors 122 in the decodersections 24'₁ -24'₈. It is also noted that signals on lines A'₀ -A'₃ andA'₀ -A'₃ are the only signals which are needed by the decoder sections24'₁ -24'₈ since the "decoding" of the bit fed to terminal A₄ is ineffect provided by selector 36' in its coupling of power to any one ofthe matrices 120a or 120b.

Having described a preferred embodiments of the invention, it is nowevident that other embodiments incorporating these concepts may be used.For example, while a 65K memory has been shown, the invention may beused with memories of greater or lesser storage capacity. Further, whenthe rows of conductors 18₀ -18₂₅₅ have been arranged in a binarypattern, a different pattern such as a Gray code pattern may be used inwhich case a bit other than the most significant bit could be used toactivate the NAND gate section selector. Further, while the memory arrayhad beeen divided into two sections, that is array section 20₁ and 20₂,larger arrays may be segmented into more sections in which case inaddition to responding to the, for example, if the array was to besegmented into four sections in addition to the section selector wouldhave to be appropriately modified to couple the power source to one ofthe four sections in response to not only the most significant bit butthe two most significant bits of the addressing signal. Further, it isfelt therefore that this invention should not be restricted to thepreferred embodiment but rather should be limited only by the spirit andscope of the appended claims.

What is claimed is:
 1. A memory circuit comprising:(a) a matrix ofmemory elements; (b) a decoder circuit responsive to an address signalfor selectively addressing the memory elements in the matrix, saiddecoder circuit having a plurality of sections for selectivelyaddressing the meory elements in different, corresponding sections ofthe matrix; (c) a decoder section selector for electrically coupling oneof the sections of the decoder to a power source while electricallydecoupling the remaining sections of the decoder from said power sourceselectively in response to the address signal; and (d) wherein thedecoder circuit comprises a plurality of gates each one thereof havingan input transistor coupled to the address signals and to the decodersection selector and an output transistor fed by the input transistorhaving an output electrode coupled to the matrix of memory elements andan additional electrode adapted for coupling to the power sourceindependent of the decoder section selector.
 2. The memory circuitrecited in claim 1 wherein the matrix of memory elements includes aplurality of non-volatile memory elements.